The eUSCI_B module supports two different ways of implementing multiple slave addresses at the same time: hardware support for up to four different slave addresses, each with its own interrupt flag and DMA trigger as well as software support for up to 2 to the power 10 different slave addresses all sharing one interrupt. The registers UCBxI2COwn Address 0, UCBxI2COA1, UCBxI2COA2, and UCBxI2COA3 contain four slave addresses. Up to four address registers are compared against a received 7 or 10-bit address. Each slave address must be activated by setting the enable bit in the corresponding address register. Register OA3 has the highest priority if the address received on the bus matches more than one of the slave address registers. The priority decreases with the index number of the address register, so that OA0 in combination with the address mask has the lowest priority. When one of the slave registers matches the 7 or 10-bit address seen on the bus, the address is acknowledged. Following this the corresponding receive or transmit-interrupt flag (UCTXIFGx or UCRXIFGx) that matches the received address is updated. The state change interrupt flags are independent of the address comparison result. They are updated according to the bus condition. The clock low timeout feature is useful for SMBus applications where a restriction has been placed on the duration for which the clock line can be held low. Using the built-in timer source allows the I²C module to perform this function without using up a system timer.