The FRAM controller is the interface between the FRAM Array and the CPU. Its function includes controlling the access speeds to FRAM to ensure that it does not exceed 8 MHz independent of the system frequency. FRAM read and writes are similar to SRAM and needs no additional special handling. The FRAM controller contains a cache with two cache sets. Each of these sets contains lines which are pre-loaded with 4 words (64 bits) during one access cycle. An intelligent logic selects one of the cache lines to pre-load FRAM data and preserves recently accessed data in the other cache. If one of the 4 words stored in a cache line is requested (also known as a cache hit), the FRAM is not accessed and the word is retrieved from the cache. However, if none of the words available in the cache are requested (also known as a cache miss), then the required instruction or data is fetched from FRAM. Access to the cache is completely transparent to the user and the usage of the cache is always enabled. In a typical application the cache hit ratio is between 66 - 75%. When the system frequency is set to higher than 8 MHz, wait-states to access FRAM need to be configured in application using the FRCTL0 register. The FRAM module also has built-in Error Correction Code (ECC) logic that is capable of detecting and correcting bit errors. There are three options for programming an MSP430 FRAM device: JTAG or the Spy-Bi-Wire interface, ROM BSL and In-system Programming. In the next section a discussion of methods to secure the device when using these methods to program the MSP430 FRAM devices will be presented.