Scheda tecnica EPC2054 di EPC

Commenti/errori della scheda tecnica

RoHS (A @ Halogen-Free 54 eGaN' FETs are supplied on Drain»SouI(e On Resistance

eGaN® FET DATASHEET

EPC2054

Maximum Ratings

PARAMETER VALUE UNIT

VDS Drain-to-Source Voltage (Continuous) 200 V

Continuous (TA = 25°C) 3A

Pulsed (25°C, TPULSE = 300 µs) 32

VGS

Gate-to-Source Voltage 6V

Gate-to-Source Voltage -4

TJOperating Temperature –40 to 150 °C

TSTG Storage Temperature –40 to 150

Static Characteristics (TJ= 25°C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.12 mA 200 V

IDSS Drain-Source Leakage VGS = 0 V, VDS = 160 V 0.001 0.1

mAIGSS

Gate-to-Source Forward Leakage VGS = 5 V 0.003 0.5

Gate-to-Source Forward Leakage#VGS = 5 V, TJ = 125°C 0.1 1

Gate-to-Source Reverse Leakage VGS = -4 V 0.001 0.1

VGS(TH) Gate Threshold Voltage VDS = VGS, ID =1 mA 0.8 1.2 2.5 V

RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 1 A 32 43 mΩ

VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.5 V

Thermal Characteristics

PARAMETER TYP UNIT

JC Thermal Resistance, Junction-to-Case 2.9

°C/WR

JB Thermal Resistance, Junction-to-Board 14

JA Thermal Resistance, Junction-to-Ambient (Note 1) 83

EPC2054 – Enhancement Mode Power Transistor

VDS , 200 V

RDS(on) , 43 mΩ

ID , 3 A

EPC2054 eGaN® FETs are supplied only in

passivated die form with solder bumps

Die Size:1.3 mm x 1.3 mm

Applications

• High Speed DC-DC conversion

• Wireless Power Transfer

• High Frequency Hard-Switching and

Soft-Switching Circuits

• Lidar/Time of Flight (ToF)

• Automation

• Solar

• Class-D Audio

Benefits

• Ultra High Efficiency

• Ultra Low RDS(on)

• Ultra Low QG

• Ultra Small Footprint

EFFICIENT POWER CONVERSION

HAL

# Defined by design. Not subject to production test.

Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.

See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details

Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very

low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG

and zero QRR. The end result is a device that can handle tasks where very high switching frequency,

and low on-time are beneficial as well as those where on-state losses dominate.

eGaN® FET DATASHEET

EPC2054

0 1 2 3 4 5 6

ID – Drain Current (A)

Figure 1: Typical Output Characteristics 25°C

VDS – Drain-to-Source Voltage (V)

VGS = 5 V

VGS = 4 V

VGS = 3 V

VGS = 2 V

RDS(on) – Drain-to-Source Resistance (mΩ)

VGS – Gate-to-Source Voltage (V)

2.0 2.5 3.0 3.5 4.0 4.5 5.0

Figure 3: RDS(on) vs. VGS for Various Drain Currents

ID = 0.5 A

ID = 1 A

ID = 1.5 A

ID = 2 A

120

100

ID – Drain Current (A)

VGS – Gate-to-Source Voltage (V)

1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Figure 2: Transfer Characteristics

25˚C

125˚C

VDS = 6 V

2.0 2.5 3.0 3.5 4.0 4.5 5.0

Figure 4: RDS(on) vs. VGS for Various Temperatures

25˚C

125˚C

ID = 1 A

RDS(on) – Drain-to-Source Resistance (mΩ)

VGS – Gate-to-Source Voltage (V)

120

100

Dynamic Characteristics (TJ = 25°C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CISS Input Capacitance#

VDS = 100 V, VGS = 0 V

358 573

CRSS Reverse Transfer Capacitance 0.3

COSS Output Capacitance#89 134

COSS(ER) Effective Output Capacitance, Energy Related (Note 2) VDS = 0 to 100 V, VGS = 0 V 120

COSS(TR) Effective Output Capacitance, Time Related (Note 3) 152

RGGate Resistance 0.8 Ω

QGTotal Gate Charge#VDS = 100 V, VGS = 5 V, ID = 1 A 2.9 4.3

QGS Gate-to-Source Charge

VDS = 100 V, ID = 1 A

0.9

QGD Gate-to-Drain Charge 0.3

QG(TH) Gate Charge at Threshold 0.7

QOSS Output Charge#VDS = 100 V, VGS = 0 V 15 23

QRR Source-Drain Recovery Charge 0

All measurements were done with substrate connected to source.

Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.

Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.

eGaN® FET DATASHEET

EPC2054

All measurements were done with substrate shortened to source.

Capacitance (pF)

1000

100

0.10 50 100 150 200

Figure 5b: Capacitance (Log Scale)

VDS – Drain-to-Source Voltage (V)

COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

ISD – Source-to-Drain Current (A)

VSD – Source-to-Drain Voltage (V)

Figure 8: Reverse Drain-Source Characteristics

25˚C

125˚C

VGS = 0 V

Capacitance (pF)

0 50 100 150 200

Figure 5a: Capacitance (Linear Scale)

VDS – Drain-to-Source Voltage (V)

COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

400

350

300

250

200

150

100

0 0.5 1.0 1.5 2.0 2.5 3.0

Figure 7: Gate Charge

VGS – Gate-to-Source Voltage (V)

QG – Gate Charge (nC)

ID = 1 A

VDS = 100 V

2.0

1.6

1.2

0.8

0.4

0.0

Figure 6: Output Charge and C

OSS

Stored Energy

100 150 200

QOSS – Output Charge (nC)

EOSS – COSS Stored Energy (µJ)

– Drain-to-Source Voltage (V)

Figure 9: Normalized On Resistance vs. Temperature

ID = 1 A

VGS = 5 V

Normalized On-State Resistance RDS(on)

2.0

1.8

1.6

1.4

1.2

1.0

0.8 0 25 50 75 100 125 150

TJ – Junction Temperature (°C)

a“ "T "T— ﬁr * "T T—I

eGaN® FET DATASHEET

EPC2054

Figure 11: Transient Thermal Response Curves

Junction-to-Board

tp, Rectangular Pulse Duration, seconds

ZθJB, Normalized Thermal Impedance

10-5 10-4 10-3 10-2 10-1 1 101

0.1

0.01

0.001

0.5

0.05

0.02

Single Pulse

0.01

0.1

0.2

Duty Cycle:

Notes:

Duty Factor: D = t1/t2

Peak TJ = PDM x ZθJB x RθJB + TB

PDM

Junction-to-Case

tp, Rectangular Pulse Duration, seconds

ZθJB, Normalized Thermal Impedance

0.5

0.1

0.05

Single Pulse

0.02

0.01

0.2

Duty Cycle:

Notes:

Duty Factor: D = t1/t2

Peak TJ = PDM x ZθJC x RθJG + TC

PDM

10-6 10-5 10-4 10-3 10-2 10-1 1

0.1

0.01

0.001

0.0001

Figure 10: Normalized Threshold Voltage vs. Temperature

Normalized Threshold Voltage

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6 0 25 50 75 100 125 150

TJ – Junction Temperature (°C)

ID =1 mA

eGaN® FET DATASHEET

EPC2054

DIE MARKINGS

Figure 12: Safe Operating Area

0.1

100

0.1 1 10 100 1000

ID – Drain Current (A)

VDS - Drain-Source Voltage (V)

Limited by RDS(on)

Pulse Width

1 ms

100 µs

10 µs

DIM Dimension (mm)

EPC2054 (Note 1) Target MIN MAX

a8.00 7.90 8.30

b1.75 1.65 1.85

c (Note 2) 3.50 3.45 3.55

d4.00 3.90 4.10

e4.00 3.90 4.10

f (Note 2) 2.00 1.95 2.05

g1.50 1.50 1.60

Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/

JEDEC industry standard.

Note 2: Pocket position is relative to the sprocket hole measured as

true position of the pocket, not the pocket hole.

Die orientation dot

Gate Pad bump is

under this corner

2054

YYYY

ZZZZ

TAPE AND REEL CONFIGURATION

4mm pitch, 8mm wide tape on 7”reel

7” reel

d e f g

Die

orientation

dot

Gate

solder bar is

under this

corner

Die is placed into pocket

solder bar side down

(face side down)

Loaded Tape Feed Direction

2054

YYYY

ZZZZ

Part

Number

Laser Markings

Part #

Marking Line 1

Lot_Date Code

Marking Line 2

Lot_Date Code

Marking Line 3

EPC2054 2054 YYYY ZZZZ

eGaN® FET DATASHEET

EPC2054

RECOMMENDED

LAND PATTERN

(measurements in µm)

Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to

improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit

described herein; neither does it convey any license under its patent rights, nor the rights of others.

eGaN® is a registered trademark of Efficient Power Conversion Corporation.

EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx

DIE OUTLINE

Solder Bump View

Side View

Seating Plane

638

120+/- 12 518+/- 25

Pad 1 is Gate;

Pad 3 is Drain;

Pads 2, 4 are Source

RECOMMENDED

STENCIL DRAWING

(measurements in µm)

Pad 1 is Gate;

Pad 3 is Drain;

Pads 2, 4 are Source

The land pattern is solder mask defined

Solder mask is 10 μm smaller per side than bump

Recommended stencil should be 4mil (100 µm) thick, must be

laser cut, openings per drawing.

The corner has a radius of R60.

Intended for use with SAC305 Type 4 solder,reference 88.5%

metals content.

Additional assembly resources available at

https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

R60

DIM Micrometers

MIN Nominal MAX

A1270 1300 1330

B1270 1300 1330

c650

d650

e250

DIM Micrometers

A1300

B1300

c650

d650

e1 230

DIM Micrometers

A1300

B1300

c650

d650

e1 230

Information subject to

change without notice.

Revised June, 2021

Scheda tecnica EPC2054 di EPC

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